Conventional X-ray imaging systems installed in hospitals and the like can be classified into a film photographing scheme which irradiates a patient with X-rays and exposes the X-rays transmitted through the patient to a film and an image processing scheme which converts X-rays transmitted through a patient into an electrical signal and executes digital image processing.
An example of apparatuses using the image processing scheme is a radiographic apparatus comprising a phosphor which converts X-rays into visible light and a photoelectric conversion device which converts the visible light into an electrical signal. The phosphor is irradiated with X-rays that have passed through a patient. The internal information of the patient, which is converted into visible light by the phosphor, is output from the photoelectric conversion device as an electrical signal. When the internal information of the patient is converted into an electrical signal, the electrical signal can be converted into digital data by an A/D converter. In this case, the X-ray image information to be used for recording, display, printing, and diagnosis can be handled as digital values.
Recently, radiographic apparatuses in which an amorphous silicon semiconductor thin film is used in a photoelectric conversion device have been put into practical use.
FIG. 24 is a plan view of a conventional photoelectric conversion substrate formed by using amorphous silicon semiconductor thin films as the materials of a MIS photoelectric conversion element 101 and switch element 102. FIG. 24 also shows interconnections that connect the elements.
FIG. 25 is a sectional view taken along a line A-B in FIG. 24. For the sake of simplicity, the MIS photoelectric conversion element will simply be referred to as a photoelectric conversion element hereinafter.
As shown in FIG. 25, the photoelectric conversion element 101 and switch element 102 (amorphous silicon TFT; to simply be referred to as a TFT hereinafter) are formed on a single substrate 103. The lower electrode of the photoelectric conversion element 101 is formed from a first metal thin-film layer 104 that is the same as the layer that forms the lower electrode (gate electrode) of the TFT 102. The upper electrode of the photoelectric conversion element 101 is formed from a second metal thin-film layer 105 that is the same as the layer that forms the upper electrode (source and drain electrodes) of the TFT 102.
The first and second metal thin-film layers 104 and 105 are also shared by a gate driving interconnection 106 and matrix signal interconnection 107 in the photoelectric conversion circuit section shown in FIG. 24. FIG. 24 shows 2×2=4 pixels. The hatched portions in FIG. 24 indicate the light-receiving surfaces of the photoelectric conversion elements 101. A power supply line 109 supplies a bias to the photoelectric conversion element 101. A contact hole 110 connects the photoelectric conversion element 101 to the TFT 102.
When the structure shown in FIG. 24, which mainly uses an amorphous silicon semiconductor, is used, the photoelectric conversion element 101, TFT 102, gate driving interconnection 106, and matrix signal interconnection 107 can be simultaneously formed on a single substrate. The photoelectric conversion circuit section having a large area can easily be provided at a low cost.
The device operation of the photoelectric conversion element 101 will be described next with reference to FIG. 26. In FIG. 26, a to c show a graph showing energy bands so as to explain the device operation of the photoelectric conversion element 101 shown in FIGS. 24 and 25.
In FIG. 26, a and b show the operations in a refresh mode and in a photoelectric conversion mode, respectively. The abscissa indicates the states of the respective layers shown in FIG. 25 in the direction of film thickness. M1 indicates a lower electrode (G electrode) formed from the first metal thin-film layer 104 of, e.g., Cr. An amorphous silicon nitride (a-SiNx) insulating thin-film layer 111 is an insulating layer that inhibits the passage of both electrons and holes. The amorphous silicon nitride insulating thin-film layer 111 must be so thick as not to generate a tunneling effect. Genarally, the thickness is 50 nm or more.
A hydrogenated amorphous silicon (a-Si:H) thin-film layer 112 is a photoelectric conversion semiconductor layer formed from an intrinsic semiconductor layer (i-layer) for which doping is intentionally unexecuted. An N+ layer 113 is an injection inhibiting layer which inhibits injection of carriers of single conductivity type. The N+ layer 113 is made of an amorphous semiconductor such as an n-type hydrogenated amorphous silicon thin-film layer that is formed to prevent hole injection to the hydrogenated amorphous silicon thin-film layer 112. M2 indicates an upper electrode (D electrode) formed from the second metal thin-film layer 105 of, e.g., Al.
Referring to FIG. 25, the D electrode serving as an upper electrode does not completely cover the N+ layer 113. However, since electrons can freely move between the D electrode and the N+ layer 113, the D electrode and N+ layer 113 always have an equipotential. A description will be done below on the basis of this condition. The device operation of the photoelectric conversion element 101 includes two operation modes, i.e., a refresh mode and a photoelectric conversion mode. These modes are based on the manner a voltage is applied to the D electrode or G electrode.
In the refresh mode shown in a of FIG. 26, a negative potential with respect to the G electrode is applied to the D electrode. Holes in the i-layer 112, which are indicated by filled circles in a of FIG. 26, are guided to the D electrode by the electric field. Simultaneously, electrons indicated by open circles in a of FIG. 26 are injected to the i-layer 112. At this time, some holes and electrons recombine in the N+ layer 113 and i-layer 112 and vanish. If this state continues for a sufficiently long time, the holes are swept from the i-layer 112.
To change the above-described state to the photoelectric conversion mode shown in b of FIG. 26, a positive potential with respect to the G electrode is applied to the D electrode. Accordingly, electrons in the i-layer 112 are instantaneously guided to the D electrode. However, holes are not guided to the i-layer 112 because the N+ layer 113 acts as an injection inhibiting layer. When light becomes incident on the i-layer 112 in this state, the light is absorbed, and electron-hole pairs are generated. The electrons are guided to the D electrode by the electric field. On the other hand, holes move through the i-layer 112 and reaches the interface between the i-layer 112 and the amorphous silicon nitride (a-SiNx) insulating thin-film layer 111. The holes cannot move into the insulating layer 111 and therefore stay in the i-layer 112. At this time, the electrons move to the D electrode while the holes move to the insulating layer interface in the i-layer. To keep the electrical neutrality in the photoelectric conversion element 101, a current flows from the G electrode. This current corresponds to the electron-hole pairs generated by light and is therefore proportional to the incident light.
After the photoelectric conversion mode shown in b of FIG. 26 is held for a certain period, the refresh mode shown in a of FIG. 26 is set again. The holes staying in the i-layer 112 are guided to the D electrode, as described above. A current corresponding to the holes flows. The number of holes corresponds to the total amount of light that becomes incident during the photoelectric conversion mode. At this time, a current corresponding to the number of electrons injected to the i-layer 112 also flows. This number is almost constant and can be detected by subtraction. That is, the photoelectric conversion element 101 can output the amount of light that becomes incident in real time and also detect the total amount of light that becomes incident during a certain period.
However, if the period of the photoelectric conversion mode becomes too long due to some reason or the illuminance of incident light is high, no current flows in some cases even when light is incident. This is because a number of holes stay in the i-layer 112, the electric field in the i-layer 112 becomes small due to these holes, generated electrons are not guided, and the electrons recombine with the holes in the i-layer 112, as shown in c of FIG. 26. This state is called the saturation state of the photoelectric conversion element 101. When the light incident state changes in this state, the current flow may be unstable. However, when the refresh mode is set again, the holes in the i-layer 112 are swept. In the next photoelectric conversion mode, a current proportional to light flows again.
As described above, if holes in the i-layer 112 should be swept in the refresh mode, all holes are ideally swept. However, an effect can be obtained even by sweeping only some holes. Since a current equal to that in the above description can be obtained, no problem is posed. That is, only the necessary thing is to prevent the saturation state shown in c of FIG. 26 in the detection opportunity in the next photoelectric conversion mode. To do this, the potential of the D electrode with respect to the G electrode in the refresh mode, the period of the refresh mode, and the characteristic of the N+ layer 113 serving as an injection inhibiting layer are defined.
In the refresh mode, electron injection to the i-layer 112 is not always necessary. In addition, the potential of the D electrode with respect to the G electrode is not limited to a negative potential. When a number of holes are staying in the i-layer 112, the electric field in the i-layer 112 is applied to guide the holes to the D electrode even when the potential of the D electrode with respect to the G electrode is positive. Furthermore, the N+ layer 113 serving as an injection inhibiting layer need not always have a characteristic to inject electrons to the i-layer 112.
FIG. 27 is a circuit diagram showing a conventional photoelectric conversion circuit corresponding to one pixel having the photoelectric conversion element 101 and TFT 102.
Referring to FIG. 27, the photoelectric conversion element 101 includes a capacitance component Ci formed from the i-layer and a capacitance component CSiN formed from the injection inhibiting layer. When the photoelectric conversion element 101 is saturated, i.e., no electric field (small electric field) is formed between the D electrode and a node N (in the i-layer), the junction (the node N shown in FIG. 27) between the i-layer and the injection inhibiting layer cannot store hole carriers because electrons and holes generated by light recombine.
That is, the potential of the node N is never higher than that of the D electrode. To embody the operation in this saturation state, a diode (D1) is connected in parallel to the capacitance component Ci in FIG. 27. That is, the photoelectric conversion element 101 has three constituent elements: capacitance component Ci, capacitance component CSiN, and diode D1.
FIG. 28 is a timing chart showing the operation of the photoelectric conversion circuit corresponding to one pixel shown in FIG. 27. The circuit operation of the pixel constituted by the photoelectric conversion element 101 and TFT 102 will be described below with reference to FIGS. 27 and 28.
A refresh operation will be described first.
Referring to FIG. 27, Vs is set to 9 V, and Vref is set to 3 V. In the refresh operation, a switch SW-A is set on the Vref side, a switch SW-B is set on the Vg(on) side, and a switch SW-C is turned on. In this state, the D electrode is biased to Vref (6 V), the G electrode is biased to the GND potential, and the node N is biased to the maximum Vref (6 V). Biasing to the maximum voltage means that if the potential of the node N is already equal to or higher than Vref in the photoelectric conversion operation before the current refresh operation, the node N is biased to Vref through the diode D1. If the potential of the node N is lower than Vref in the preceding photoelectric conversion operation, the node N is not biased to the potential Vref by the current refresh operation. In actual use, when the photoelectric conversion operation was repeated a plurality of number of times in the past, the node N is substantially biased to Vref (6 V) by the current refresh operation.
After the node N is biased to Vref, the switch SW-A is switched to the Vs side. Accordingly, the D electrode is biased to Vs (9 V). With this refresh operation, hole carriers stored in the node N of the photoelectric conversion element 101 are swept to the D electrode side.
An X-ray irradiation period will be described next.
As shown in FIG. 28, a subject is irradiated with X-rays as pulses. A phosphor Fl is irradiated with the X-rays that have passed through the subject to be detected so the X-rays are converted into visible light. The semiconductor layer (i-layer) is irradiated with the visible light from the phosphor Fl so the visible light is photoelectrically converted. Hole carriers generated by photoelectric conversion are stored in the node N and increase its potential. Since the TFT 102 is OFF, the potential on the G electrode side increases by the same amount.
The wait period is inserted between the refresh period and the X-ray irradiation period. This period is a standby period in which no elements are operated, and any operation is inhibited until relaxation when the characteristic of the photoelectric conversion element 101 is unstable due to, e.g., a dark current immediately after the refresh operation. When the characteristic of the photoelectric conversion element 101 does not become unstable immediately after the refresh operation, the wait period need not be prepared.
A transfer operation will be described next.
In the transfer operation, the switch SW-B is set on the Vg(on) side to turn on the TFT 102.
Accordingly, electron carriers (Se) corresponding to the number (Sh) of hole carriers stored upon X-ray irradiation flow from a C2 side to the G electrode side through the TFT 102 to increase the potential of the read capacitor C2. At this time, Se and Sh hold Se=Sh×CSiN/(CSiN+Ci). The potential of the read capacitor C2 is simultaneously amplified and output through an amplifier. The TFT 102 is kept ON for a time enough to transfer the signal charges and then turned off.
A reset operation will be described finally.
In the reset operation, the switch SW-C is turned on, and the read capacitor C2 is reset to the GND potential to prepare for the next transfer operation.
FIG. 29 is a two-dimensional circuit diagram of the conventional photoelectric conversion device.
For the descriptive convenience, FIG. 29 illustrates only 3×3=9 pixels. Reference symbols S1-1 to S3-3 denote photoelectric conversion elements; T1-1 to T3-3, switch elements (TFTs); G1 to G3, gate interconnections to turn on/off the TFTs (T1-1 to T3-3); and M1 to M3, signal interconnections. A Vs line is an interconnection to apply a storage bias or refresh bias to the photoelectric conversion elements S1-1 to S3-3.
The electrode on the solid side of each of the photoelectric conversion elements S1-1 to S3-3 is a G electrode. A D electrode is formed on the opposite side. The D electrodes share part of the Vs line. To send light, a thin N+ layer is used as the D electrodes. The entire structure including the photoelectric conversion elements S1-1 to S3-3, TFTs (T1-1 to T3-3), gate interconnections G1 to G3, signal interconnections M1 to M3, and Vs line is called a photoelectric conversion circuit section 100.
The Vs line is biased by a power supply Vs or power supply Vref. The power supplies are switched by a control signal VSC. A shift register SR1 applies a driving pulse voltage to the gate interconnections G1 to G3. The voltage that turns on the TFTs (T1-1 to T3-3) is externally supplied. The voltage to be supplied is defined by the power supply Vg(on).
A read circuit section 200 amplifies the parallel signal outputs from the signal interconnections M1 to M3 in the photoelectric conversion circuit section 100, converts the parallel signals into serial signals, and outputs them.
Reference symbols RES1 to RES3 are switches which reset the signal interconnections M1 to M3; A1 to A3, amplifiers which amplify the signals from the signal interconnections M1 to M3; CL1 to CL3, sample-and-hold capacitors which temporarily store the signals amplified by the amplifiers A1 to A3; Sn1 to Sn3, switches to execute sample-and-hold operations; B1 to B3, buffer amplifiers; Sr1 to Sr3, switches to convert the parallel signals into serial signals; SR2, a shift register which supplies a pulse for serial conversion to the switches Sr1 to Sr3; and Ab, a buffer amplifier which outputs the serially converted signals.
FIG. 30 is a timing chart showing the operation of the photoelectric conversion device shown in FIG. 29. The operation of the photoelectric conversion device shown in FIG. 29 will be described below with reference to this timing chart.
A control signal VSC applies biases of two types to the Vs line, i.e., the D electrodes of the photoelectric conversion elements S1-1 to S3-3. When the control signal VSC is “Hi”, the D electrode is set to Vref(V). When the control signal VSC is “Lo”, the D electrode is set to Vs(V). The read power supply Vs(V) and refresh power supply Vref(V) are DC power supplies.
The operation during the refresh period will be described first.
All signals in the shift register SR1 are set to “Hi”, and the CRES signal in the read circuit section 200 is set to “Hi”. Accordingly, all the TFTs (T1-1 to T3-3) for switching are turned on. In addition, the switch elements RES1 to RES3 in the read circuit section 200 are also turned on. The G electrodes of all the photoelectric conversion elements S1-1 to S3-3 are set to the GND potential. When the control signal VSC changes to “Hi”, the D electrodes of all the photoelectric conversion elements S1-1 to S3-3 are biased to the refresh power supply Vref (negative potential). All the photoelectric conversion elements S1-1 to S3-3 are set in the refresh mode, and refresh is performed.
A photoelectric conversion period will be described next.
When the control signal VSC switches to “Lo”, the D electrodes of all the photoelectric conversion elements S1-1 to S3-3 are biased to the read power supply Vs (positive potential). The photoelectric conversion elements S1-1 to S3-3 are set in the photoelectric conversion mode. In this state, all the signals in the shift register SR1 are set to “Lo”, and the CRES signal in the read circuit section 200 is set to “Lo”. Accordingly, all the TFTs (T1-1 to T3-3) for switching are turned off. In addition, the switch elements RES1 to RES3 in the read circuit section 200 are also turned off. The G electrodes of all the photoelectric conversion elements S1-1 to S3-3 are set in a DC open state. However, the potential is held because the photoelectric conversion elements S1-1 to S3-3 also have capacitance components as constituent elements.
At this time, since no light is incident on the photoelectric conversion elements S1-1 to S3-3, no charges are generated. That is, no current flows. When the light source is turned on to emit a pulse, the D electrodes (N+ electrodes) of the photoelectric conversion elements S1-1 to S3-3 are irradiated with light, and a so-called photocurrent flows. The light source is not particularly illustrated in FIG. 29. For, e.g., a copying machine, a fluorescent lamp, LED, or halogen lamp is used. For an X-ray imaging apparatus, an X-ray source is used literally. In this case, a scintillator that converts X-rays into visible light is used. The photocurrent generated by the light is stored in the photoelectric conversion elements S1-1 to S3-3 as charges. The charges are held even after the light source is turned off.
A read period will be described next.
A read operation is performed in the order of the photoelectric conversion elements S1-1 to S1-3 of the first row, the photoelectric conversion elements S2-1 to S2-3 of the second row, and the photoelectric conversion elements S3-1 to S3-3 of the third row.
First, to read the photoelectric conversion elements S1-1 to S1-3 of the first row, a gate pulse is applied from the shift register SR1 to the gate interconnection G1 of the switch elements (TFTs) T1-1 to T1-3. At this time, the high level of the gate pulse equals the externally supplied voltage V(on). Accordingly, the TFTs (T1-1 to T1-3) are turned on. Signal charges stored in the photoelectric conversion elements S1-1 to S1-3 are transferred to the signal interconnections M1 to M3.
Although not particularly illustrated in FIG. 29, a read capacitor is added to each of the signal interconnections M1 to M3. The signal charges are transferred to the read capacitors through the TFTs (T1-1 to T1-3). For example, the read capacitor added to the signal interconnection M1 corresponds to the sum of (three) interelectrode capacitances (Cgs) between the gates and sources of the TFTs (T1-1 to T3-1) connected to the signal interconnection M1. The signal charges transferred to the signal interconnections M1 to M3 are amplified by the amplifiers A1 to A3. The capacitor corresponds to C2 shown in FIG. 27. When the CRES signal is turned on, the signal charges are transferred to the sample-and-hold capacitors CL1 to CL3 and held when the CRES signal is turned off.
When a pulse is applied from the shift register SR2 to the switches Sr1, Sr2, and Sr3 in this order, the signals held by the sample-and-hold capacitors CL1 to CL3 are output from the buffer amplifier Ab in the order of the sample-and-hold capacitors CL1, CL2, and CL3. As a result, photoelectric conversion signals of one row including the photoelectric conversion elements S1-1, S1-2, and S1-3 are sequentially output. The read operation of the photoelectric conversion elements S2-1 to S2-3 of the second row and the read operation of the photoelectric conversion elements S3-1 to S3-3 of the third row are executed in the same way as described above.
When the signals of the signal interconnections M1 to M3 are sampled and held by the sample-and-hold capacitors CL1 to CL3 in accordance with a SMPL signal of the first row, the signal interconnections M1 to M3 can be reset to the GND potential by the CRES signal. After that, a gate pulse can be applied to the gate interconnection G2. That is, while the signals of the first row are serially converted by the shift register SR2, the signal charges in the photoelectric conversion elements S2-1 to S2-3 of the second row can be simultaneously transferred in the shift register SR1.
With the above operation, the signal charges of all the photoelectric conversion elements S1-1 to S3-3 of the first to third rows can be output.
The above-described operation of the X-ray imaging apparatus is an operation for acquiring one still image by executing the refresh operation, irradiating the subject with X-rays, and executing the read operation. To acquire continuous moving images, the timing chart shown in FIG. 30 is repeatedly executed a number of times corresponding to the desired number of moving images.
However, to particularly obtain moving images by using an X-ray imaging apparatus with an enormous number of pixels, the frame frequency must be further increased. If the refresh operation of photoelectric conversion elements is executed through a Vs line common to all the photoelectric conversion elements, one refresh period must be essentially provided in one frame. This decreases the frame frequency, i.e., decreases the operation speed especially in acquiring moving images.
Generally, specifications necessary for simple imaging of a breast part should include an imaging area of 40 cm square or more and a pixel pitch of 200 μm or less. If an X-ray imaging apparatus is constructed with an imaging area of 40 cm square and a pixel pitch of 200 μm, 4,000,000 photoelectric conversion elements are necessary. When such a large number of pixels are refreshed at once, the current that flows in the refresh mode becomes large. Since the voltage variation in GND or power supply line of the X-ray imaging apparatus increases, no stable imaging can be executed.
For an image of a certain type required, an X-ray irradiation standby time must be provided until the voltage variation relaxes. Although not illustrated in FIG. 30, the standby time corresponds to the wait period shown in FIG. 28. That is, to refresh all photoelectric conversion devices at once, one refresh period is necessary in one frame, and additionally, one wait period is necessary in one frame.